Video Display Controller via OpenRISC ASIC chip fundraiser

Post here to discuss generating video signals.

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Chuckt
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Video Display Controller via OpenRISC ASIC chip fundraiser

Post by Chuckt » Sun Jan 20, 2013 12:48 pm

I found a .PDF on a chip that has a Video Controller and I googled the "Chrontel CH7301C HDMI driver" because it appeared in the .pdf and this page came up:

http://www.chrontel.com/index.php/products

The information came from an "OpenRISC ASIC chip fundraiser" which is an ASIC which probably contains the I.P. of the Chrontel HDMI driver:
“We are raising $250,000 to build the worlds first truly open source system on chip processor. Help make this happen by donating to the project today.

Money raised will be used to fabricate a batch of OpenRISC SOC ASIC chips that will be available for sale to individuals and product manufacturers.

The processor will be affordable, and competitive in mobile and embedded applications. The 32 bit RISC chip will run at an estimated 250Mhz, support Video, DDR2 Memory, Gigabit Ethernet, USB, Audio, Serial, PCI and run the Linux operating system. Individual processors will be sold for an estimated $5 per unit."
The processor will be affordable, and competitive in mobile and embedded applications. The 32 bit RISC chip will run at an estimated 250Mhz, support Video, DDR2 Memory, Gigabit Ethernet, USB, Audio, Serial, PCI and run the Linux operating system. Individual processors will be sold for an estimated $5 per unit.
http://openriscday.org/

I looked at page 3 of their .pdf on the chip's video controller capabilities and I found:
2.2 Display controller

The OpenCores VGA/LCD Controller core is a WISHBONE revB.3 compliant embedded VGA
core capable of driving CRT and LCD displays. It supports user programmable resolutions
and video timings, which are limited only by the available WISHBONE bandwidth. Making it
compatible with almost all available LCD and CRT displays

The core supports a number of color modes, including 32bpp, 24bpp, 16bpp, 8bpp gray-scale,
and 8bpp-pseudo color. The video memory is located outside the primary core, thus providing
the most flexible memory solution. It can be located on-chip or off-chip, shared with the systems
main memory (VGA on demand) or be dedicated to the VGA system. The color lookup table

Chapter 2: Block Diagram 4

is, as of core version 2.0, incorporated into the color-processor block.
Pixel data is fetched automatically via the Wishbone revB.3 Master interface, making this
an ideal program-and-forget video solution. More demanding video applications like streaming
video or video games can benefit from the video-bank-switching function, which reduces flicker
and cluttered images by automatically switching between video-memory pages and/or color
lookup tables on each vertical retrace.

The core can interrupt the host on each horizontal and/or vertical synchronization pulse. The
horizontal, vertical and composite synchronization polarization levels, as well as the blanking
polarization level are user programmable.

IP available from OpenCores: http://opencores.org/project,vga_lcd
http://cdn.opencores.org/pdf/or1k-asic.pdf

So it might be possible to include this chip in your micrcontroller project if the fundraising is complete and a success. There may also be a lot involved that I do not know but I don't know what it can do unless I try.

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