I was reading through the ADC with digital ports project and started thinking, at what voltage level does the port pin read a logic 0?
As the CAP discharges and the port eventually reads the logic 0, I am sure that point is not 0 volts.
The only thing I could find in the PIC16F648A data sheet that gives an indication is in the DC Characteristics (section 17.4) on page 140.
My guess is that it is either the Input Low Voltage (VIL), or the Input High Voltage (VIH).
The reason I ask this is, I think by calculating the correct R/C time constant to reach the "logic 0" with the pot at full resistance "and"
knowing the voltage threshold for the port pin to trigger a HIGH/LOW state, then there would be no need for calibrating.
For instance, by calculating the R/C time constant so at full resistance it will take 200mS to reach the trigger level and read logic 0, the count variable can be set up accordingly then divided by 8 such as you did. Then every 25mS will increase the LED to the next level.
I have not yet tried this but does it sound logical to you?
I am thinking the only way to make it work is to know the level at which it reaches logic 0 so you can calculate the correct time but that may not be necessary.